Sr. Verification Engineer jobs - Santa Clara, CA

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Apr 20 Sr ASIC Verification Engineer Intel Santa Clara, CA

and capabilities in ASIC Performance Verification and Reliability domain.Job responsibilities include: Supporting ICF ASIC customers both in Pre-sales evaluation phase and... more

Apr 19 Senior & Principal Asic Verification Engineer Job Juncture Mountain View, CA

to have a real impact. Principal ASIC Verification Engineer (Mountain View, CA., ... level, ASIC functional verification engineer.Responsible for the development of... more

Apr 19 Digital Verification Engineer, Sr II Synopsys Sunnyvale, CA

of R&D Engineer, Sr II is a Senior Digital Verification Engineer, focusing on functional ... test/verification plans; developing verification environments and testing suites... more

Apr 18 Sr Layout Verifications Engineer Intel Santa Clara, CA

support experience with commercial physical verification tools (ICV Calibre - DRC, LVS, RCX) as applied to digital, analog and mixed signal designs in sub-micron CMOS... more

Apr 16 SENIOR & PRINCIPAL ASIC VERIFICATION ENGINEER Cameron Craig Group Mountain View, CA

to have a real impact. Principal ASIC Verification Engineer (Mountain View, CA., ... level, ASIC functional verification engineer. Responsible for the development of... more

Apr 01 Senior IC Design/Verification Engineer Atmel San Jose, CA

Senior IC DesignVerification Engineer San Jose, CA USA Atmel Corporation (Nasdaq ATML) is ... Work with digital designers and verification engineers to design and test... more

Mar 29 Senior Logic Verification Engineer Teledyne Technologies Santa Clara, CA

We are looking for an experienced Logic (FPGA and/or ASIC) Verification Enginees who has t ... Ethernet, Fibre Channel, etc.* Hands-on verification development using SystemVerilog,... more

Dec 10 Sr Architect - Verification Acceleration Cadence Design Systems San Jose, CA

senior R&D architect to help develop verification acceleration technology. The senior architect will lead a small team of highly experienced individuals in developing behavioral... more

Dec 10 Sr. Verification Engineer Cadence Design Systems San Jose, CA

This position is for a Senior Verification Engineer in the Silicon development group at ... familiarity of constrained random verification methodology. - Knowledge and... more

Oct 17 SR Digital Design & Verification Engineer - jm7213 Imaging Sensors Palo Alto, CA

JM7213 Engineer, Digital Design & Verification Location:Palo Alto, CA Local candidates ... experience with RTL coding in Verilog, verification, validation, synthesis, timing... more

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