Synopsys jobs - Mountain View, CA

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Apr 17 SENIOR DFT ENGINEER NVIDIA Santa Clara, CA

and at-speed testing.- Experience with Synopsys Tetramax.- Experience in Logic Design, Verilog RTL, verification and static timing analysis.- Experience with simulation tools such... more

Apr 15 Design-for-Test Technical Manager (TTI SJ 2014 19) Tsmc Na San Jose, CA

Tetramax, DFT Complier, Synopsys SMS, Tessent MBIST, Boundary Scan * Experience with conference publication and patent filing (desired) * Experience with Perl, TCL and shell... more

Apr 14 Corporate Application Engineer (Synthesis) Mentor Graphics Fremont, CA

Test, FormalPro, RealTime Designer), Synopsys (Design Compiler (DCT/DCG), IC Compiler, PrimeTime, Formality ), Cadence (SoC Encounter, RTL Compiler, Conformal ), and Magma... more

Apr 12 ASIC Physical Design Engineer Encore Semi Milpitas, CA

required:• Strong knowledge of Synopsys design flow including IC Compiler and PrimeTime SI• Understanding of deep sub-micron design problems and solutions, including leakage... more

Apr 08 Principle Lead Logic IC Design Engineer Di11731 Los Altos, CA

top-level design. - Hands-on experience with Synopsys tools is a plus. - Logic synthesis with Synopsys Design Compiler is a plus. Visit our website at httpwww.photonic-corp.com!... more

Mar 13 Software Engineer Staff Juniper Networks Sunnyvale, CA

Responsibilities ABOUT JUNIPER NETWORKS Juniper Networks is in the business of network innovation. From devices to data centers, from consumers to cloud providers, Juniper... more

Mar 11 Senior Design Engineer Middlesex Community College San Jose, CA

one synthesis, place and route flow. Synopsys Design Compiler/IC Compiler, Cadence EDI or Magma Talus. * Strong and detailed understanding of P&R methodology, especially routing... more

Mar 06 Senior Design Engineer Artisan San Jose, CA

one synthesis, place and route flow. Synopsys Design Compiler/IC Compiler, Cadence EDI or Magma Talus. * Strong and detailed understanding of P&R methodology, especially routing... more

Mar 04 SMTS Design Enablement (P&R) (58363) Globalfoundries US Santa Clara, CA

with digital implementation tools and flows (Synopsys ICC, Cadence EDI, Mentor OlympusSoC) and/or design rule implementation for physical verification or layout construction... more

Feb 06 Staff Digital Hardware Design Engineer Xilinx San Jose, CA

industry-standard EDA tools from Cadence, Synopsys or Mentor * Simulation experience with Cadence IES and experience building block level verification suites * Understanding of... more

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