Synopsys jobs - Mountain View, CA

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Apr 15 Senior Customer Engagement Engineer, Product Engineering (8912) Cadence Design Systems San Jose, CA

Area Posted 28 days ago * Synopsys Sr. Corporate Applications Engineer - DDR PHY San Francisco Bay Area Posted 12 days ago * Product Support Engineer Tier 3 San Francisco... more

Apr 10 MTS, PDK Design Enablement Engineer Globalfoundries Santa Clara, CA

LVS tools* 2+ years experience in Synopsys StarRC, CadenceQRC and/or other industry-standard PEX tools* Familiarity with advanced semiconductor manufacturing processes* Experience... more

Apr 09 Order Mgmt Analyst, I Synopsys Sunnyvale, CA

Provides timely order acceptance and maintain an accurate backlog. Responsible for reviewing and interpreting customer contracts to ascertain the level of compliance to corporate... more

Apr 08 Principle Lead Logic IC Design Engineer Di11731 Los Altos, CA

top-level design. - Hands-on experience with Synopsys tools is a plus. - Logic synthesis with Synopsys Design Compiler is a plus. Visit our website at httpwww.photonic-corp.com!... more

Mar 28 Sr ASIC Verification Engineer Job Intel Santa Clara, CA

is desired and also the ability to ram up on synopsys based flows. Qualifications Position Qualifications : o Must have an MS in Electrical or Computer Engineering with 7+ years... more

Mar 21 Foundry Design Kits - CAD, Design Automation, and Applications Engineers Intel Santa Clara, CA

analysis tools and flows o Experience with Synopsys or Cadence ASIC tools is desired o ... ASIC design, custom IC design oExpertise in Synopsys and Cadence tools and flows for ASIC... more

Mar 11 Technical Marketing Manager Middlesex Community College San Jose, CA

Hands-on understanding of Synopsys & Cadence implementation flows (RTL to GDSII) including low power flows • Understanding of full chip STA including multiple power domains •... more

Mar 06 Technical Marketing Manager Artisan San Jose, CA

Hands-on understanding of Synopsys & Cadence implementation flows (RTL to GDSII) including low power flows • Understanding of full chip STA including multiple power domains •... more

Mar 04 SMTS Design Enablement (P&R) (58363) Globalfoundries US Santa Clara, CA

with digital implementation tools and flows (Synopsys ICC, Cadence EDI, Mentor OlympusSoC) and/or design rule implementation for physical verification or layout construction... more

Feb 26 Senior Emulation Engineer Apple Santa Clara, CA

(EVE, Cadence Palladium, Mentor Veloce, Synopsys HAPS, other FPGA/ASIC-based emulator) of a high-performance processor or SOC * Strong programming (C/C++) and scripting skills... more

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