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Apr 15 Compose synopses for top movies, tv shows, and video games Temporary Contract Palo Alto, CA

Hello, We are looking for top notch writing talent to compose synopses for popular movies, tv shows, and video games. You must have a strong command of the english language and be... more

Apr 12 Design for Test Manager Tandem Recruiting Group San Jose, CA

DFT FastScan, Tetramax, DFT Complier, Synopsys SMS, Tessent MBIST, Boundary Scan Experience with conference publication and patent filing (desired) Experience with Perl, TCL and... more

Apr 10 Sr. Level GPU Engineering Experts Needed (in the following areas) Silicon Valley Resources San Jose, CA

skills, Verilog. Familiarity with Synopsys synthesis and timing.• Verification ... Verilog background. Familiarity w/ Synopsys DV tools and/or UVM and/or formal... more

Apr 10 Testability Design Engineer, Principle Lead Photonic-corp Los Altos, CA

Successful track record of delivering products to production. - Experience with full-chip testability design.- Hands-on experience with Synopsys tools is a plus. Visit our... more

Apr 09 Principle IC Testability Design Engineer Apic Los Altos, CA

design. - Hands-on experience with Synopsys tools is a plus. Visit our website at!! VLSI 65 nm testability manycore ARM... more

Apr 02 VLSI analog layout / CAD engineer San Jose, CA

parasitic extraction using Cadence QRC and Synopsys StarRC.- Skilled at top level layout of full chips.- Experience with power analysis, IR drop measurement, power planning.-... more

Mar 26 CFM Defect Engineer-Semiconductor Globalfoundries US San Jose, CA

CFM Defect Engineers – Multiple Openings Senior Defect Engineer, Contamination Free Manufacturing (CFM) Principal Process Engineer Defect Data Management (CFM) GLOBAL FOUNDRIES is... more

Mar 21 Place and Route Technical Engineer or Manager Tandem Recruiting Group San Jose, CA

entation Advanced timing optimization methodology Be an expert in ASIC RTL-to-GDS design flow, 20- 28nm technology, coding with TCL/perl, synopsys/cadence tools, multi-million... more

Mar 17 Senior DFT Engineer Collabera San Jose, CA

Test or Mentor Fastscan ATPG tools, Synopsys DFTC scan insertion.Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.Working knowledge in one... more

Mar 02 ASIC DFT Engineer Saispringtech Sunnyvale, CA

should have strong experience with Synopsys flow. We use Virage tools to generate MBIST code. The person should have good RTL skills to write the required RTL in addition... more

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