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Apr 17 CAD Engineer, Design Verification Apple Santa Clara, CA

Must be very experienced with Synopsys VCS or NC-Verilog, or Modelsim. * Strong scripting abilities in PERL are needed, TCL or Python is a plus. * Must be conversant in VHDL. *... more

Apr 15 Design-for-Test Technical Manager (TTI SJ 2014 19) Tsmc Na San Jose, CA

Tetramax, DFT Complier, Synopsys SMS, Tessent MBIST, Boundary Scan * Experience with conference publication and patent filing (desired) * Experience with Perl, TCL and shell... more

Apr 10 Engineer, UVM Verification - IC Design Broadcom Sunnyvale, CA

and debug tools from Cadence, Synopsys (VCS, Verdi) and Mentor• Strong communication and presentation skills• Experience with working with diverse teams worldwideCountry United... more

Apr 09 Research internship in Microarchitecture Lab Intel Santa Clara, CA

skills and experience:* >System Verilog and Synopsys tools* >Familiarity with Linux, Windows and Android programming environments*Job Category:* Engineering*Primary Location:*... more

Mar 21 Sr. Staff, IC Design Engineer Broadcom San Jose, CA

Lint tools • Synthesis using Synopsys tool suite • Timing Analysis using Synopsys Primetime tool • Formal Verification • DFT concepts of Scan, BIST. • Strong Perl and Tcl... more

Mar 13 Software Engineer Staff Juniper Networks Sunnyvale, CA

Responsibilities ABOUT JUNIPER NETWORKS Juniper Networks is in the business of network innovation. From devices to data centers, from consumers to cloud providers, Juniper... more

Mar 13 SENIOR DFT ENGINEER NVIDIA Santa Clara, CA

and at-speed testing. - Experience with Synopsys Tetramax. - Experience in Logic Design, Verilog RTL, verification and static timing analysis. - Experience with simulation tools... more

Mar 11 Staff Engineer - Technical Files Middlesex Community College San Jose, CA

Synopsys Design Compiler/IC Compiler, Cadence EDI or Magma Talus. • Strong and detailed understanding of P&R methodology, especially routing algorithms and DRCs. • Strong... more

Mar 06 Senior Design Engineer Artisan San Jose, CA

one synthesis, place and route flow. Synopsys Design Compiler/IC Compiler, Cadence EDI or Magma Talus. * Strong and detailed understanding of P&R methodology, especially routing... more

Feb 10 Emulation Engineer-Temporary - Engineer II Mindlance San Jose, CA

hardware design languages - Experience using Synopsys and Xilinx FPGA tools - Self-starter with the ability to work in a close-knit team environment - Experience with both Windows... more

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