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Apr 13 Senior Design Engineer ( PCIe & DDR ) Quantum Solution Santa Clara, CA

ufacturing, and/or DFD would be an added advantage Experience with Synopsys VCS, Cadence Incisive, Mentor Modelsim Experience with Synopsys Design Compiler and/or Physical... more

Apr 12 Design for Test Manager Tandem Recruiting Group San Jose, CA

DFT FastScan, Tetramax, DFT Complier, Synopsys SMS, Tessent MBIST, Boundary Scan Experience with conference publication and patent filing (desired) Experience with Perl, TCL and... more

Apr 10 Testability Design Engineer, Principle Lead Photonic-corp Los Altos, CA

Successful track record of delivering products to production. - Experience with full-chip testability design.- Hands-on experience with Synopsys tools is a plus. Visit our... more

Apr 10 Sr. Level GPU Engineering Experts Needed (in the following areas) Silicon Valley Resources San Jose, CA

skills, Verilog. Familiarity with Synopsys synthesis and timing.• Verification ... Verilog background. Familiarity w/ Synopsys DV tools and/or UVM and/or formal... more

Apr 09 Principle IC Testability Design Engineer Apic Los Altos, CA

design. - Hands-on experience with Synopsys tools is a plus. Visit our website at!! VLSI 65 nm testability manycore ARM... more

Apr 02 VLSI analog layout / CAD engineer San Jose, CA

parasitic extraction using Cadence QRC and Synopsys StarRC.- Skilled at top level layout of full chips.- Experience with power analysis, IR drop measurement, power planning.-... more

Mar 31 EDA Engineers- Place/Route tools CAE Recruiters San Jose, CA

in Synopsys, Cadence and/orMentor SOC implementation and sign-off flows.- strong CAD automation using: Makefile, Tcl/Tk, PERL, HTML, C++.- Proficient in UNIX and PerlEducational... more

Mar 25 Digital Design Engineer (Multimedia) Collabera Santa Clara, CA

Linting, Synopsys synthesis, Formal Verification, CDC, Power ArtistHave owned and handled designs ~500K gates.Excellent communication skillsEducation:Master's Preferred, BSEE with... more

Mar 13 UVM verification Innovative LOGIC San Jose, CA

checking tools Jasper, Cadence (IEV) and Synopsys (Magellan) verification management tools as well as understanding of database management Prior experience with silicon debug at... more

Mar 02 ASIC DFT Engineer Saispringtech Sunnyvale, CA

should have strong experience with Synopsys flow. We use Virage tools to generate MBIST code. The person should have good RTL skills to write the required RTL in addition... more

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