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Apr 12 Design for Test Manager Tandem Recruiting Group San Jose, CA

DFT FastScan, Tetramax, DFT Complier, Synopsys SMS, Tessent MBIST, Boundary Scan Experience with conference publication and patent filing (desired) Experience with Perl, TCL and... more

Apr 10 Testability Design Engineer, Principle Lead Photonic-corp Los Altos, CA

Successful track record of delivering products to production. - Experience with full-chip testability design.- Hands-on experience with Synopsys tools is a plus. Visit our... more

Apr 10 Sr. Level GPU Engineering Experts Needed (in the following areas) Silicon Valley Resources San Jose, CA

skills, Verilog. Familiarity with Synopsys synthesis and timing.• Verification ... Verilog background. Familiarity w/ Synopsys DV tools and/or UVM and/or formal... more

Apr 09 Principle Lead Logic IC Design Engineer Apic Los Altos, CA

top-level design. - Hands-on experience with Synopsys tools is a plus. - Logic synthesis with Synopsys Design Compiler is a plus. Visit our website at httpwww.photonic-corp.com!... more

Apr 09 Principle IC Testability Design Engineer Apic Los Altos, CA

design. - Hands-on experience with Synopsys tools is a plus. Visit our website at httpwww.photonic-corp.com! httpwww.photonic-corp.com! VLSI 65 nm testability manycore ARM... more

Apr 06 Critique of Vietnam War-era screenplay Temporary Contract Castro Valley, CA

BY INVITATION ONLY. Seek producer-caliber notes on a feature-length screenplay running 113 pages, plus a one-page synopsis and one-page query letter. Familiarity with Vietnam War... more

Mar 25 Digital Design Engineer (Multimedia) Collabera Santa Clara, CA

Linting, Synopsys synthesis, Formal Verification, CDC, Power ArtistHave owned and handled designs ~500K gates.Excellent communication skillsEducation:Master's Preferred, BSEE with... more

Mar 21 Place and Route Technical Engineer or Manager Tandem Recruiting Group San Jose, CA

entation Advanced timing optimization methodology Be an expert in ASIC RTL-to-GDS design flow, 20- 28nm technology, coding with TCL/perl, synopsys/cadence tools, multi-million... more

Mar 17 Senior DFT Engineer Collabera San Jose, CA

Test or Mentor Fastscan ATPG tools, Synopsys DFTC scan insertion.Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.Working knowledge in one... more

Mar 13 UVM verification Innovative LOGIC San Jose, CA

checking tools Jasper, Cadence (IEV) and Synopsys (Magellan) verification management tools as well as understanding of database management Prior experience with silicon debug at... more

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